(1) Field of the Invention
The present invention relates to a process for making storage capacitors for random access memory (RAM) devices, and more specifically for making improved RAM capacitors in recesses in shallow trench isolation (STI) with overlying gate electrodes for increased circuit density on 1T-SRAM cells. The 1T-SRAM cells are used in system-on-a-chip (SoC) technologies. The method of this invention utilizes a novel node photoresist mask for plasma etching recesses in the STI that prevents plasma-etch-induced defects in the substrate. This novel photoresist mask also provides bottle-shaped capacitor structures which maximizes capacitance while concurrently reducing the surface topography over the capacitor top electrodes. This reduced topography results in reduced leakage currents when the gate electrodes are formed over the capacitor top electrodes for increased circuit density.
(2) Description of the Prior Art
Static random access memory (SRAM) and Dynamic random access memory (DRAM) devices are widely used in integrated circuits in the electronics industry to store binary data. In these volatile memory devices the conventional SRAM utilizes six transistors to store each bit of binary data (1 or 0), while the DRAM uses a single charge stored on a capacitor, and one transfer transistor. The SRAM is fast but is of relatively low bit density, while the much smaller DRAM cell switches relatively slowly and requires frequent refresh cycles to maintain the charge on the capacitor. In recent years a new type of circuit design has been developed that uses a single transistor and single capacitor (commonly referred to a 1T-SRAM) to replace the more conventional six-transistor SRAM bit cell. The 1T-SRAM is described in more detail in the article titled “The Ideal SoC Memory: 1T-SRAM,” W. Leung et al., pages 32–36 in Proceedings of the IEEE 2000, and the novel features are also described in U.S. Pat. No. 6,256,248 B1 and U.S. Pat. No. 6,468,855 B2 to Leung et al. In Leung's approach the bit lines are kept short and are made of metal, which reduces the ratio of the bit line to memory cell capacitance. This allows for smaller cell capacitors to be made in and on the substrate than is required for the more conventional DRAM. In addition, the array of small fast memory banks (multiBank) and the shorter word lines utilized in the 1T-SRAM device further reduce the cycle time.
One method of increasing memory cell density is to form word lines (gate electrodes) that extend over the RAM stacked capacitor in the STI recesses. However, there are several structure problems and processing problems which are described with respect to FIGS. 1 and 2. A schematic cross section showing a portion of a substrate 10 having a partially completed RAM capacitor in a recess is shown in FIG. 1. As shown in FIG. 1, after forming STI regions 12 in a substrate 10, a pad oxide 14, and a hard-mask layer are formed. Using a photoresist mask 18, openings 1 for bottom electrodes are plasma etched into the STI regions 12. Unfortunately, when the openings (not shown) in the photoresist mask extend over the edge of the substrate 10 (active device areas), the plasma etching, indicated by the vertical arrows 19 in FIG. 1, damages the substrate in the region X. This results in leakage currents that can degrade the RAM memory device.
A second problem associated with making these types of RAM capacitors is depicted in FIG. 2. After etching recesses 1 (see FIG. 1) in the STI 12, bottom electrodes 20 are formed. An interelectrode layer 22, top electrodes 24, and as cond hard mask 26 (insulating layer) are formed to complete the capacitor. Unfortunately, during processing a crevice C is formed in th recesses, and when the word lines 32 are formed over the top electrodes 24, the second hard-mask layer 26 provides poor insulation between the word line and the top electrode resulting in electrical shorts S in the crevice C, as depicted in FIG. 2.
A method for making a deep trench capacitor is described in U.S. Pat. No. 4,713,678 to Womack et al. Womack does not address making word lines over the capacitor. Chen et al., U.S. Pat. No. 6,420,226 B1 describe a method for making a buried stacked capacitor structure in a shallow trench but do not address making word lines that extend over the capacitors. Schrems in U.S. Pat. No. 6,580,110 B2 describes making deep trench capacitors in a silicon substrate, but does not address forming stacked capacitors in a STI.
Therefore, there is still a strong need in the industry to make buried stacked capacitors in shallow trench recesses with improved structures having word lines extending over the capacitors for increased circuit density.